Ever larger scales of integration in integrated circuits are normally accompanied by a constant decrease in the supply voltage for the integrated circuits. In this context, certain integration technologies may use semiconductor components with different supply voltages. By way of example, CMOS (Complementary Metal Oxide Semiconductor) production techniques use transistors for designing analog circuits, particularly for forming interfaces for the integrated circuit, with a comparatively high withstand voltage in addition to transistors which are suitable for designing digital circuits and have a significantly lower withstand voltage.
In order to supply integrated circuits, which need various supply voltages internally, with just one external supply voltage, there is normally an “on-chip” voltage regulator, which is usually in the form of a continuously operating linear regulator. In this case, such voltage regulators should be able to manage without external inductances or capacitances.
Particularly when actuating resonant circuits, for example in order to generate radio-frequency carrier signals, a voltage regulator whose output voltage has good supply voltage suppression (Power Supply Rejection Ratio, PSRR) and at the same time has low inherent noise is desired in order to supply the voltage controlled oscillators which are normally provided in that case, so as not to impair the phase noise in the oscillator which is to be powered.
The document V. R. von KAENEL, A high-speed, low-power clock generator for a microprocessor application, IEEE Journal of Solid-State Circuits, Vol. 33, No. 11, November 1998 specifies a phase locked loop in a clock generator, which phase locked loop shows a generalized illustration of a voltage regulator using a circuit diagram, cf. FIG. 2 therein.
The paper G. W. Den Besten, B. Nauta, Embedded 5 V-to-3.3 V Voltage Regulator for Supplying Digital ICs in 3.3 Volt CMOS Technology, IEEE Journal of Solid-State Circuits, Vol. 33, No. 7, July 1998 specifies a voltage regulator for converting an input voltage of 5 volts into an output voltage of 3.3 volts in CMOS circuitry. FIGS. 2a and 2b show ordinary voltage regulators which use either a P-channel MOS transistor, cf. FIG. 2a, or an N-channel MOS transistor, cf. FIG. 2b, as regulating transistor. The gate connection of the regulating transistor is respectively actuated by a difference amplifier, to which firstly a reference voltage, which is provided by a bandgap circuit, for example, and secondly a signal derived from the regulator's output voltage are supplied. Although the circuit variant with the PMOS transistor provides a large voltage control range, it has the drawback of inadequate supply voltage suppression at frequencies above the amplifier bandwidth. Although the regulator circuit with the NMOS transistor exhibits good PSRR properties, it has a relatively low achievable output voltage.
If the regulating transistor in a circuit in line with FIG. 2a or 2b in the latter document is equipped with a withstand voltage which is lower than the input voltage of the voltage regulator, then, particularly in the case of a resistive-capacitive load mixture, turning on the voltage regulator may result in a voltage drop across the regulating transistor which is larger than its admissible voltage. If the difference amplifier used, which actuates the regulating transistor, is a bandgap voltage source, whose voltage first needs to build up starting at 0 volt, then even the full input voltage is applied across the regulating transistor at the instant-of turning on.